RESISTIVE DEVICE FOR MEMORY OR LOGIC CIRCUIT AND METHOD FOR MANUFACTURING SUCH A DEVICE

专利摘要:
The invention relates to a resistive device comprising: - a substrate (100); a plurality of electrically conductive pillars (110) disposed on the substrate and spaced from each other, each conductive pillar (110) having a smaller base section than at its top - a plurality of storage elements (120); ) of variable electrical resistance arranged at the vertices of the conductive pillars, so that each storage element (120) is supported by one of the conductive pillars (110).
公开号:FR3027453A1
申请号:FR1460073
申请日:2014-10-20
公开日:2016-04-22
发明作者:Bernard Dieny；Maxime Darnon；Gabrielle Navarro；Olivier Joubert
申请人:Centre National de la Recherche Scientifique CNRS；Commissariat a lEnergie Atomique CEA；Universite Joseph Fourier (Grenoble 1)；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
IPC主号:

专利说明:

[0001] The present invention relates to a resistive device of the nonvolatile memory type or of the logic type, comprising a plurality of variable electrical resistance storage elements known as resistive devices of the nonvolatile memory type or of the logic type, comprising a plurality of variable electrical resistance storage elements. also memory points or logical units.
[0002] STATE OF THE ART Several non-volatile memory technologies are being developed with various degrees of maturity. It is possible in particular to mention phase change random access memory (PCRAM) memories, resistive conductor bridge (CBRAM) conductive bridge memories or OxRAM oxide based memories, ferroelectric FeRAM memories and magnetic memories M RAM. Apart from the FeRAM memories which operate on the principle of the orientation of an electric dipole moment in a ferroelectric material, all other memories use variable electrical resistance materials. Each bit of information is stored in a variable resistance element and encoded by the resistance value of this storage element (typically logic level '0' corresponds to a high resistance value and logic level '1' corresponds to a low resistance value).
[0003] The mechanism behind the variation in resistance depends on the technology used. In the PCRAM for example, it is semiconductor chalcogenide materials that can be passed from an amorphous state to a crystalline state (or vice versa) by current pulses of appropriate amplitude and duration. In MRAMs, the storage element is a magnetic tunnel junction with a tunnel magnetoresistance effect. In CBRAMs, conductive filaments are formed or destroyed by diffusing metal species (eg Ag) into a semiconductor matrix (eg Ge). All these forms of memory involve the passage of a current through the storage element, which has an electrical resistance varying between a minimum value and a maximum value.
[0004] In microelectronics, one of the techniques commonly used to etch materials in industrial processes is reactive plasma etching. This reactive plasma etching usually forms volatile compounds by reaction between the etched material and the constituents of the plasma (conventionally based on C12, HBr, SF6, CF4, O2, NH3, CO, CH3OH, etc.), these volatile compounds being then pumped out of the burning enclosure. The problem encountered with the materials of the MRAM memories (various magnetic and non-magnetic materials constituting the magnetic tunnel junction, for example Pt, Pd, CoFe, NiFe, CoFeB, PtMn, IrMn, MgO and NiO), CBRAMs (chalcogenides of type GeSbTe or InSbTe) and some OxRAM (CaTiO3, PrCaMnO3 and other transition metal oxides) is the absence of volatile compounds or, on the contrary, an excessively reactive etching of the materials which makes the dimensional control difficult (GeSbTe case in particular) and modifies the properties of the materials (for example the crystallization speed of GeSbTe). When the etching residues are not volatile, they can not be evacuated and redeposit on the substrate being etched. These residues also tend to line the walls of the engraving frame, leading to problems of reproducibility and defectivity. In addition, the gases used to generate the reactive plasma can corrode the materials to be etched. The etching of these "memory" materials can also be carried out by bombarding ions of neutral gas, typically argon. However, this technique, called ion beam etching (Ion Beam Etching, IBE), gives results of insufficient quality for an industrial process. Indeed, several problems arise: - The IBE etching technique leads to a large number of defects at the edges of the structures that form the storage elements and to a significant variability of electrical or magnetic properties from one memory point to another . - The etching residues are not volatile, they pollute the substrate and the etching frame, like the plasma etching. In particular, they are deposited on the flanks of the structures, which alters the electrical properties of the storage elements. For example, in the case of a magnetic tunnel junction, the etching of the upper magnetic electrode may result in metal deposition on the sidewalls of the structure which bypasses the tunnel barrier. - The storage elements engraved by IBE have inclined sides, which is troublesome for high density applications where the memory points are very close to each other. - Uniform etching on substrates with a diameter greater than or equal to 300 mm is difficult to obtain because the flow of ions is not homogeneous on such a surface. No solution has so far been found to etch satisfactorily the materials of the storage elements used in non-volatile memories MRAM, OxRAM and CBRAM, in particular those of resolution less than 30 nm. Moreover, the same problems arise in the field of logic components, and more particularly magnetic logic units MLU (Magnetic Logic Unit) which each comprise a magnetic tunnel junction engraved by IBE or reactive plasma etching.
[0005] The "damascene" method is an alternative to plasma etching (IBE or reactive plasma) for structuring the storage elements of the MRAM, CBRAM and OxRAM memories. This method, usually used for the manufacture of metal interconnections of integrated circuits, consists of defining the imprint of the element in an insulating material, then depositing the materials (magnetic, chalcogenides, oxides ... depending on the memory technology referred to ) on the entire substrate. Chemical mechanical polishing removes excess material outside the footprint.
[0006] Document US6153443 gives an example of MRAM memory obtained by the "damascene" method. Each memory point consists of a magnetic tunnel junction connected to a selection transistor via a via and a metal line. The transistor is made in conventional CMOS technology, while the via and the tunnel junction are made using the "damascene" method. The different layers of the tunnel junction are deposited in cavities previously formed in an insulating material.
[0007] Thus, the "damascene" method makes it possible to dispense with the etching of the memory materials. However, the successive deposits of materials on the sides of the cavities reduce the effective surface of the storage element and make it difficult to control the thickness of the layers deposited on these flanks. This is particularly true for MRAMs which can stack a large number of magnetic and non-magnetic layers of very small thickness, the tunnel barrier layer having for example a thickness of the order of 1 nm. If the thickness of the barrier layer becomes too low at the flanks of the cavities, electrical short circuits can appear through this barrier making the tunnel junction unusable.
[0008] All the structuring methods described above generate in the memory points (or logical points) a large number of structural and / or chemical defects, which lead to a high variability of point-to-point properties, in particular a strong dispersion of electrical properties. and retention of the memory point (i.e., its ability to keep the information over time). This dispersion is all the stronger as the size of the points is small, since the defects appear most of the time at the periphery of the points. SUMMARY OF THE INVENTION There is therefore a need to provide a resistive device whose variable electrical resistance storage elements have a reduced density of structural or chemical defects, leading to a lower variability of the electrical and retention properties between the elements of the device. storage.
[0009] According to the invention, there is a tendency to satisfy this need by providing a resistive device comprising a substrate, a plurality of electrically conductive pillars disposed on the substrate and spaced from one another, and a plurality of variable electrical resistance storage elements arranged at the tops of the conductive pillars, so that each storage element is supported by one of the conductive pillars. Each driver pillar has a section at its base smaller than its top.
[0010] In a preferred embodiment, the conductive pillars have flanks covered with a layer of electrically insulating material. The device according to the invention may also have one or more of the following characteristics, considered individually or in any technically possible combination: the section of each conductive pillar varies in a continuous and strictly increasing manner from the base to the top of the conductive pillar ; the substrate comprises a dielectric layer traversed by interconnection patterns above which the conductive pillars are located; the substrate comprises a dielectric layer traversed by interconnection patterns, said interconnection patterns extending further outside the dielectric layer to form the conductive pillars; the conducting pillars are separated from each other by a dielectric material; the storage elements are formed of a stack of the MRAM, PCRAM, CBRAM, OxRAM or MLU logic type; the substrate comprises first and second portions on which the conductive pillars are distributed, the storage elements of the first portion being of the MRAM type and the storage elements of the second portion being of the confined PCRAM type.
[0011] Another aspect of the invention relates to a method of manufacturing such a resistive device. This method comprises the following steps: depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching through the mask the first conductive layer, so as to obtain a plurality of electrically conductive pillars spaced from each other and having a section at their base smaller than their top; forming, by physical vapor deposition, variable electrical resistance storage elements at the vertices of the conductive pillars, so that each storage element is supported by one of the conductive pillars. Alternatively, the manufacturing method may comprise the following steps: forming vertical damascene-type interconnection structures of electrically conductive material on a substrate, said vertical interconnection structures being distributed within a dielectric layer and having a section at their base weaker than at their summit; thinning the dielectric layer so as to at least partially release said vertical interconnection structures; and - by vapor phase physical deposition of the variable electrical resistance storage elements at the vertices of the vertical interconnection structures, so that each storage element is supported by one of the vertical interconnection structures. BRIEF DESCRIPTION OF THE FIGURES Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limitative, with reference to the appended figures, among which: FIG. embodiment of a resistive device with flared pillars according to the invention; FIG. 2 represents a second embodiment of a resistive device with flared pillars according to the invention; FIG. 3 schematically represents a substrate on which the resistive device according to the invention can be manufactured; FIGS. 4A to 4G represent steps F1 to F7 of a method of manufacturing a resistive device according to the invention; FIG. 5 illustrates an alternative embodiment of steps F6 and F7; FIG. 6 represents an example of a resistive device in which the flared pillars are formed by "damascene" type interconnection structures, according to a third embodiment of the invention; FIGS. 7A to 7C show steps F1 'to F3' of a method of manufacturing the resistive device according to the third embodiment of the invention; FIG. 8 represents another example of a resistive device in which the flared pillars are of "damascene" type, manufactured by the "double damascene" method; FIGS. 9A to 9C show the formation of a first example of a storage element having a local thickness variation; FIGS. 10A and 10B show the formation of a second example of a storage element having a local variation in thickness; FIGS. 11A and 11B show the formation of a first example of a storage element exhibiting a local variation of chemical composition; FIGS. 12A and 12B show the formation of a second example of storage element exhibiting a local variation of chemical composition; FIGS. 13A to 13F represent steps S1 to S6 of a method of manufacturing a hybrid resistive device MRAM / PCRAM confined according to the invention; FIG. 14 represents two adjacent memory points of the MRAM / PCRAM hybrid resistive device confined according to the sectional plane A-A of FIG. 13F; and FIG. 15 represents an implementation variant of step S5 of FIG. 13E. For the sake of clarity, identical or similar elements are marked with identical reference signs throughout the figures.
[0012] DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT In the following description, the term "resistive material" is used to describe the material or materials that constitute the variable resistance storage element. It may be a conductive material playing the role of electrode or active material, that is to say the one that performs the function of storage (or memory). In order to more easily structure the storage elements, and thus to obtain elements of better quality, a substrate having a plurality of electrically conductive mesa-shaped pillars is used. These pillars, or pads, are spaced from each other and have overhanging flanks, so that when depositing each resistive material of the storage element, the layer of this material is discretized at the tops of the pillars and between the pillars . In other words, this substrate makes it possible to naturally structure the storage elements at the vertices of the pillars, without the need to etch the resistive material posteriorly. The pillars have a flared shape (at least partially) and a section at their base smaller than at their top. They are sufficiently electrically isolated from each other, despite the presence of resistive material at the bottom of the trenches separating the pillars, thanks to the fact that the material does not cover the flanks at the base of the pillars. Indeed, the deposition of the resistive material being effected by a substantially directional process, preferably by physical vapor deposition (PVD) such as sputtering or evaporation, the upper part overhanging each pillar prevents the effect of shading the deposition of the material at the foot of the flanks. Since the step of etching the resistive material by IBE or plasma etching is dispensed with, the storage elements contain fewer structural or chemical defects on the edges (usually caused by IBE or reactive plasma etching).
[0013] Therefore, the resistive device according to the invention has less variability from one memory point to another in terms of performance. In addition, the storage elements are not likely to be corroded as is generally the case with reactive plasma etching. Their side walls can be vertical, rather than inclined, because of the absence of etching residues.
[0014] Finally, as will be described in detail below, the fact of depositing the resistive material on previously etched studs allows to play on the deposition bearings, in order to create lateral gradients of thickness or chemical composition at scale of each plot. Figure 1 shows, in sectional view, a first embodiment of a resistive device where the variable resistance storage elements are supported by flared and conductive pillars. The resistive device comprises a substrate 100 on which is disposed a set of pillars 110 of electrically conductive material, for example tantalum. The pillars 110 are oriented vertically relative to the plane of the substrate 100. Preferably, their section, measured in a plane parallel to the substrate 100, varies in a strictly increasing manner from the base to the top of the pillars. In other words, the section of the pillars 110 is minimal at their base and maximum at their apex. The device further comprises a plurality of storage elements 120 arranged at the vertices of the pillars 110. In the case of memory-type applications, these storage elements 120 exhibit an electrical resistance varying between two states, a weakly resistive state and a state strongly resistive, in response to an electrical stimulus. They can therefore form memory points (CBRAM type, MRAM, OxRAM ...) or logical units (including magnetic). They may be formed of one or more layers, the material or materials of which vary according to the nature of the device to be produced, for example according to the type of memory envisaged. In the case of memristor-type applications, intermediate values of the resistor are used between the weakly resistive state and the highly resistive state.
[0015] Each storage element 120 is supported by one of the conductive pillars 110. Preferably, the resistive device comprises as many pillars 110 as there are storage elements 120, that is to say memory cells ( for memory applications) or logical units (for logical applications). The pillars 110 are preferably of identical shape and size. They are generally arranged in rows and columns on the substrate 100, to form a matrix of memory points. Above each storage element 120, the resistive device advantageously comprises a cover element 130 made of electrically conductive material, which makes it easier to make electrical contact at the level of the storage element 120. Like the storage element, this element Cover element 130 is limited to the upper face of pillar 110 which supports it. The material of the covering elements 130 may be identical or different from that of the conductive pillars 110. Finally, an electrical contact 140 is disposed on each covering element 130 and makes it possible to convey the current to the storage element 120 (by way of intermediate of the cover element 130).
[0016] As shown in FIG. 1, the vertical structures formed by the conductive pillars 110, the storage elements 120 and the superposed covering elements 130 are advantageously embedded in a dielectric material 150 which reinforces the solidity from a mechanical point of view of the set of pillars and storage elements, and which also allows the realization of the electrical contact at the top of the layer 130. Finally, there remains on the substrate 100 residual deposits 160 of (x) resistive material ( s) forming the storage elements 120. These residual deposits 160 have an irregular shape due to the shading effects created by the projecting edges of the pillars 110. They are located between the conductive pillars 110 and are electrically inactive. They do not disturb the operation of the device. In this first embodiment, the sides of the pillars 110 have a notch profile. The section of each pillar 110 is firstly constant in a lower portion of the pillar, then increases abruptly in its upper part, near the top. This variation of section can be continuous, as illustrated in FIG. 1, or discontinuous. FIG. 2 represents a second embodiment, in which the sidewalls of the pillars 110 have an arcuate shape or "barrel" ("bowing") and are covered with a layer 200 of electrically insulating material. The section of the pillars varies continuously, for example by increasing from the base to the top of the pillars as shown in Figure 2. Otherwise, the section may slightly decrease from the base of the pillars then increase as and when that we are getting closer to the summit. In other words, the minimum section of the pillars is not necessarily that at the base of the pillars.
[0017] More generally, the pillars can be of various shapes depending on the technology used. In particular, their section may be round, elliptical, square or rectangular. The insulating layer 200 covers at least the flank portion located at the base of the pillars 110, facing the residual deposits 160 of resistive material, and preferably all of the flanks. It improves the electrical insulation between the various pillars 110. It is particularly advantageous when the flanks are slightly overhanging, that is to say when the section at the top is only slightly greater than the section at the base. In this situation, the residual deposit 160 located between two adjacent pillars 110 may be substantial and, if one does not pay attention to the choice of the dielectric material 150, there is a risk of short circuit between these two pillars. This risk (or the constraints on the choice of the dielectric material 150) is here eliminated by means of the insulating layer 200. On the other hand, when the sidewalls are strongly overhanging, the insulating layer 200 is not mandatory, since the residual deposit 160 is further away from the pillars 110. To prevent the residual deposit 160 between the pillars does not touch the base of the pillars 110, it is preferable that the vertical projection in the plane of the substrate of the widest section of each pillar exceeds from minus 2 nm in all directions from the pillar section to its base. This value may depend on the directivity of the deposit of the resistive element but constitutes a lower limit for the case of a relatively directive deposit such as that obtained by evaporation. It is then in the situation where the insulating layer 200 on the sides of the pillars 110 is optional - because the insulation (spacing between pillars and residual deposit) is already sufficient. Furthermore, in this second embodiment, the device comprises a protective layer 210 located at the vertices of the pillars 110, at the interface between each pillar 110 and the corresponding storage element 120. This protective layer 210 prevents, when forming the layer 200 on the sides of the pillars 110, to simultaneously produce an insulating material on their upper face. In other words, the protective layer ensures electrical continuity between each conductive pillar 110 and the storage element 120 disposed on this upper face. It is preferably formed of a noble metal or an electrically conductive oxide / nitride, for example ruthenium oxide (RuO). The specificities of each embodiment, described above in relation to FIGS. 1 and 2, can of course be combined in them. For example, the sides of the pillars 110 may be notched and covered with the insulating layer 200. A method of manufacturing a resistive device according to any one of these embodiments will now be described. reference to Figures 3, 4A to 4G. Figure 3 shows the substrate 100 which serves as a starting point for the manufacturing process, while Figures 4A to 4G show steps F1 to F7 of this method. The substrate 100 conventionally comprises a CMOS circuit capable of addressing each memory point and reading the data recorded in the storage element, ie the electrical resistance value of this element. This circuit comprises for example selection transistors electrically connected to the conductive pillars by one or more levels of interconnection. In FIG. 3, only the last level of interconnection before the memory points is shown in cross section. It is formed of a layer of dielectric material 101 (for example 512 or A1203) traversed by interconnection patterns 102, such as via conductors or conductive lines, typically metal (copper, aluminum ...). These interconnection patterns 102 make it possible to electrically connect the storage elements to the CMOS circuit.
[0018] For non-volatile memory applications, it is generally sought to integrate the storage elements as high as possible in the stack, to optimize the manufacturing process. Preferably, the conductive pillars of the resistive device are formed over one of the last metal levels. The via conductors (or conductive lines) 102 are (in current technologies) typically separated by a distance d greater than or equal to 3F, where F denotes the resolution of the resistive device, that is to say the minimum dimension achievable by lithography ("half-pitch" in English). This value of 3F corresponds for example to CMOS technology at the distance separating two via consecutive emerging MOSFET transistors. The substrate 100 which supports the pillars 110 generally occupies the entire surface of the memory circuit to be manufactured. However, in the case of a hybrid memory / logic circuit, the substrate 100 may correspond to only a portion of the circuit. The rest of the circuit is then protected during the manufacturing of the memory points by an insulating material or by a sacrificial material, which will be removed during or at the end of the circuit manufacturing process.
[0019] Of course, like any metal level of the substrate, the interconnection level of Figure 3 may comprise other patterns (type via or line) than those for electrically connecting the pillars 110 (and referenced 102). For example, these other patterns can connect a lower level to a higher level than the storage elements or two MOS transistors located lower in the substrate. In the case of lines, they are not necessarily traversing. The steps F1 to F7 described below in relation to FIGS. 4A to 4G make it possible to produce, on this starting substrate 100, resistive nanostructures connected in series with the via conductors 102 and isolated from each other.
[0020] Step F1 of Figure 4A consists of depositing on the substrate 100 an electrically conductive layer 300 of thickness h. This layer 300 is intended to form the conductive pillars after being etched.
[0021] The thickness h of the layer 300 is advantageously greater than the cumulative thickness of the storage elements 120 and the covering elements 130 making it possible to make electrical contact above the memory point (see FIG. Thus, the excess material 160 between the pillars 110 is located below the storage element 120. The thickness h is preferably between 4 nm and 400 nm. For example, in MRAMs based on magnetic tunnel junctions, the tunnel junction has a thickness of 10 nm to 30 nm and the cover material can be 100 nm thick. In this case, the thickness h is significantly greater than 130 nm, and preferably greater than 180 nm. Furthermore, the electrical conductivity of the material of the layer 300 is such that, once etched in the form of mesa, the electrical resistance of each pillar is low, typically less than the maximum resistance of the storage element or memory point. This minimizes the parasitic series resistance effect which decreases the relative signal variation when reading the state of the memory point (weakly or strongly resistive). For example, the memory point is formed by a magnetic tunnel junction, which can be characterized from an electrical point of view by the product "Resistance x Area" or "RA". The product RA is a function of the thickness of the tunnel barrier (for example, an insulating layer of MgO) and the energy height of this barrier. Moreover, by making the approximation that the section A of a pillar is uniform over all its height h, the electrical resistance Rt of the pillar is written: p. h Rt = -A where p is the electrical resistivity of the conductive layer 300. A much lower rt resistance than that of the storage element constituting the memory point is then equivalent to the relation ph "RA, ie p" RA / h. The tunnel junctions used in MRAMs (Spin Transfer Torque MRAM), typically have RA values of the order of 10 0.11 m 2.
[0022] With a thickness h of about 50 nm, this implies on the electrical resistivity of the layer 300 the following condition: p "2.10 A.cm. The material of the conductive layer 300 may be chosen from tantalum (Ta), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiN) and polycrystalline silicon (poly- Si) strongly doped (concentration of dopants for example greater than 5.1018 cm-3 for phosphorus doping). All of these materials fulfill the resistivity condition above. According to an alternative embodiment, the conductive layer 300 may be replaced by a stack of several conductive layers having characteristics similar to those described above, especially from the point of view of the electrical resistivity. An advantageous example of stacking is described below, in relation with FIG. 4D. In step F2 of FIG. 4B, an etching mask 310 is formed on the conductive layer 300. In a conventional manner, the etching mask 310 may consist of a photosensitive resin, structured by lithography, or of a material more resistant to etching than the photosensitive resin - in this case it is called "hard mask". The hard mask is, for example, silicon oxide (5iO2), silicon nitride (Si3N4), silicon oxynitride (SiON) or amorphous carbon.
[0023] The solid portions of the mask 310 constitute patterns 311 located vertically above the via conductors 102 (or conductive lines) of the substrate 100 and have the shape of the storage elements that are to be made. Advantageously, each pattern 311 is centered with respect to the underlying conductive via 102 and has dimensions greater than those of the via, so that the later formed pillar completely covers it. For example, the patterns 311 may have a width L approaching 2F (Fig.4B). Thus, when the via 102 are periodically spaced a distance equal to 3F, the edge-to-edge distance of the adjacent patterns 311 is of the order of F. The shape of the patterns 311 is preferably round for reasons of homogeneity of electrical properties over the entire periphery of the pillars and to facilitate the realization of the device at the most advanced technological nodes (sub20nm). Nevertheless, other forms can be envisaged, in particular square, elliptical and rectangular.
[0024] In F3 (FIG. 4C), the conductive layer 300 is etched through the mask 310. The etching technique used during this step F3 is preferably a reactive plasma etching. Indeed, it allows (in the case of the metal or polysilicon of the layer 300) to obtain volatile etching residues that can be easily removed by pumping out of the etching reactor. The etching conditions are here determined so as to obtain conductive pillars 110 with overhanging sides, for example according to a notched (Fig.1) or arcuate (Fig.2) profile. Highly isotropic etching should be avoided to prevent etching under the patterns of the mask 310, which would reduce the dimensions of the top face of the pillars (and thus storage elements). All the aforementioned materials can be etched with reactive plasma based on fluorine (except aluminum) or chlorine (including aluminum), or even bromine. The need to make recessed flanks requires etching chemistry that can give rise to spontaneous reactions between the material and the etching gas. Chlorine-containing gases, such as HCl, Cl 2 and BCl 3, or fluorine such as SF 6, NF 3, CF 4, will therefore preferably be chosen. It is also possible to use mixtures of chlorine-based and fluorine-based gases, or mixtures of chlorine and bromine-based gases (for example, HBr is a bromine source) to create an arcuate profile. or in "barrel", while avoiding over-etching under the patterns 311 of the mask 310, the reactive etching conditions may be chosen as follows: the power of the radiofrequency electromagnetic field which generates the plasma is advantageously between 150 W and 500 W, to limit the formation of radicals based on chlorine; the bias voltage applied to the substrate holder is preferably between 15 V and 1 kV, and advantageously less than 200 V.
[0025] These parameters can be adjusted, especially during engraving, to control the curvature of the arc. For example, an increase in the RF power makes it possible to increase the concentration of radicals and thus to increase the curvature. An increase in the polarization power tends to reduce the chemical component of the etching and thus reduce the amplitude of the barrel. The addition of a diluent gas (Ar, Xe, He, N2 ...), to reduce the concentration of chlorine in the gas phase, or the addition of a passivating gas, tends to make the plasma less reactive and therefore to reduce the spontaneous etching reactions that create the curvature of the flanks.
[0026] To create a notched profile, a two or three step etching process can be used. During the first step, the upper portion of the layer 300 (typically 50% of its thickness) is etched anisotropically to obtain vertical flanks. These vertical flanks are obtained thanks to the gradual formation of a passivation layer on the walls of the etched patterns, this passivation layer then preventing lateral etching. During the last step, isotropic etching is performed to etch the remaining portion of the layer 300, vertically towards the substrate 100 but also laterally.
[0027] The upper part of the layer 300 is protected by the passivation layer previously formed during the first etching step. Advantageously, an intermediate oxidation step is carried out to reinforce the passivation layer. By way of example, a doped polysilicon slot pillar can be obtained by inductively coupled plasma etching based on HBr / Cl 2 / O 2 (110 sccm / 70 sccm / 2 sccm) with an ion energy between of 70 eV and 80 eV, followed by etching by a plasma based on Cl2 and SF6 (60 sccm / 3 sccm) with an energy of ions of the same order of magnitude. In the case of a conductive layer 300 made of TiN, the first etching step can be carried out with an inductively coupled plasma based on HBr / Cl 2 (100 sccm / 50 sccm), followed by an intermediate step of plasma etching. 02-based inductive probe for oxidizing the flanks, and finally an inductively coupled plasma etching based on Cl2 (possibly preceded by an identical plasma with highly energetic ions 50 eV) to remove the titanium oxide from the etching edge) .
[0028] After obtaining pillars 110 to the desired shape, the etching mask 310 can be removed, preferably wet (for example in a solution of hydrofluoric acid).
[0029] An alternative for notch pillar formation is to employ two superimposed layers of different materials instead of a single conductive layer 300. The top layer material is then etched anisotropically while the layer material is etched. inferior is etched isotropically, without changing the profile of the upper layer. Non-exhaustive examples include the following layer stacks (upper layer / lower layer): doped Si / Al; Al / Si doped, Si doped / TiN, TiN / Al, TiN / VV, Al / W, Ru / TiN, Ru / Ti, Ru / Ta, Ru / TaN and doped Ru / Si.
[0030] For example, an Al / VV stack may be etched with an inductively coupled BC13 / Cl2 plasma for aluminum and then with an SF6 based inductively coupled plasma for tungsten. In the case of a Si / TiN stack, the silicon can be etched with an HBr / C12 / 02 based inductively coupled plasma and then the titanium nitride can be etched with an inductively coupled plasma based on dichlor (Cl2). The ruthenium of an Ru / Si stack can be etched by an inductive plasma based on oxygen and chlorine or hydrogen chloride (HCl). A dilution gas such as Ar, H2, N2 or He may optionally be added to the gas phase of the plasma. The RF power injected into the source is preferably between 150 W and 1500 W and the polarization power can vary between 20 W and 300 W, preferably between 20 W and 50 W, in order not to consume too much the hard mask and the underlying doped silicon layer at the end of ruthenium etching. The silicon layer can then be etched using an inductively coupled SF6 or NF3 plasma, optionally diluted with argon or helium.
[0031] In a preferred embodiment represented by FIG. 4D, the method also comprises a step F4 for forming the insulating layer 200 on the sidewalls of the pillars 110. As has been described previously, this step is recommended in order to avoid short-circuits between the conductive pillars 110, while limiting the constraints on the dimensions of the pillars and the choice of the dielectric material separating the pillars. The insulating layer 200 can be obtained in different ways. A first technique consists in forming against the side walls of the pillars 110 dielectric spacers identical or similar to those used in the gate structures of the MOS transistors. These spacers are preferably formed by atomic layer deposition ("Atomic Layer Deposition", ALD). This technique of the microelectronic industry has the advantage of being able to produce conformal deposits, even here on barrel-shaped or notched flanks. The possible materials are for example Si3N4, HfO2, ZrO2 or A1203. After deposition of the spacers, the thickness of which may be between 2 nm and 5 nm, an etching step makes it possible to eliminate the material of the spacer at the apexes of the pillars 110. Preferably, selective etching processes will be chosen with respect to material constituting the pillars 110. It is indeed necessary to minimize the damage to their upper face, which will receive a variable electrical resistance storage element. It is also possible to use a sacrificial material (such as SiO 2 or Si 3 N 4) whose chemical nature is different from that of the spacer, to protect this surface during etching of the spacer. The hard mask 310 can also play this protective role, in which case it is removed only after forming the insulating layer 200, not before. According to an alternative embodiment, the insulating layer 200 is obtained by oxidation or nitriding of the material constituting the pillars 110. In other words, the sidewalls of the insulating pillars can be made from the electrical point of view by exposing them to oxygen. or nitrogen. An oxygen or nitrogen plasma can be used to make this oxidation or nitriding more efficient. For the same purpose, the substrate can be heated between 20 ° C and 450 ° C.
[0032] During this oxidation / nitriding step, the upper face of the pillars 110 is also affected if it is not protected. Thus, in order to avoid the formation of an insulating material on this upper face, which would lead to problems of reading / writing of the memory point, it is possible, as previously, to preserve the etching mask 310 during the oxidation / nitriding step. and remove it only after, or deposit another so-called sacrificial protective material, such as a silicon nitride (SiN, Si3N4, SiOCN, SiNH) or a silicon oxide (5i02). The protective material is subsequently removed to make the upper face of the pillars 110 conductive again. Of course, the removal method is chosen so that it does not affect the insulating layer 200 that has just been formed on the flanks. Pillars 110. For example, in the case of a nitride tantalum on the flanks, a sacrificial layer 522 on the upper face can be removed by a solution of hydrofluoric acid.
[0033] An alternative is the use of a stack of several sub-layers instead of a single layer 300. As specified in step F1, the layer 300 may be replaced by two materials, preferably two metals, having different properties . Two cases occur: the so-called protective top material is insensitive to oxidation or nitriding, for example it is a noble metal, and the lower material which forms the pillars 110 is capable of forming a oxide or nitride (Ta, W, Al, Ti, TiN, Si ...). In this way, the upper material will be conductive while the flanks of the lower material will be insulating. The etching of the noble metal, in step F3, may require another etching technique than that used for the material of the pillars 110, for example the ion beam etching ("Ion Beam Etchnig", IBE). - The lower and upper materials are both likely to form an oxide or nitride, but the latter have different electrical behavior: the oxide / nitride of the upper material is conductive and the oxide / nitride of the lower material is insulating. By way of example, ruthenium (Ru) or chromium (Cr), the oxides of which are conductive, or titanium (Ti), the nitride of which is conductive, in combination with Ti, TiN, Ta, may be used as the upper material. , Si, Al or W whose oxide is insulating, or with Si or Ta whose nitride is insulating. Of course, when the spacer technique is used to form the insulating layer 200, it is not necessary to use a protective layer of chromium, ruthenium or noble metal. FIG. 4E diagrammatically represents a step F5 in which the resistive material of the storage elements is firstly deposited at the tops of the pillars 110, and in a second step the material of the covering elements 130 makes it possible to make electrical contact. . Sputtering is advantageously used in the deposition step F5. This technique has a certain directivity for directing the deposition of resistive material to the pillars 110, especially at their summit. However, resistive material and roofing material are also deposited at the bottom of the trenches located between the pillars 110, or even on a portion of the sidewalls of the pillars depending on the incidence of the deposit and the angular dispersion of the flow of atoms from the target. sprayed, then forming residual deposits 160. At normal incidence relative to the surface of the substrate (as shown in Figure 4E), these residual deposits 160 are located around the center of the trenches. The more the flanks of the pillars 110 are overhanging, the less the deposits 160 extend near the base of the flanks. In oblique incidence (case not shown), the deposits 160 may be located on one and the same side of the pillars 110, or on all sides of the pillars if the substrate is rotated during deposition. The formation of recessed flanks therefore prevents the simultaneous deposition of resistive material on two flanks facing each other and belonging to different pillars, which avoids a short circuit between these two pillars. Preferably, the cathodic sputtering is collimated in order to increase the directivity of the deposit and thus reduce the extent of the residual deposits 160 at the bottom of the trenches. The deposits 160 can be left as they are. Thanks to the electrical discontinuity on the sides of the pillars 110, they do not significantly disturb the operation of the resistive device. In particular, they do not create inter-pinch short circuits. The formation of the storage elements 120 at the vertices of the pillars 110 may comprise the deposition of one or more materials, depending on the technology of memories or logical elements envisaged. For example, to make a MRAM magnetic tunnel junction, a reference layer (eg a Co, Fe and B-based alloy), a tunnel barrier layer (eg MgO) and a storage layer are successively deposited. (eg an alloy containing Co, Fe and B, with concentrations identical to or different from those of the reference layer). The reference layer and the storage layer are (ferro) magnetic, while the tunnel barrier layer is non-magnetic. The storage layer may be located above or below the tunnel barrier, the reference layer being located on the other side of the tunnel barrier with respect to the storage layer. The tunnel junction is generally covered by the covering element 130. The different layers of the storage elements 120 may be deposited by different techniques and at different incidences (see Figs.9 to 12). For a PCRAM memory and a ReRAM memory (OxRAM, CBRAM), the deposited material is respectively a phase change material and a resistive oxide inserted between conductive electrodes. In the case of MRAMs, it is generally sought to maximize the surface of the magnetic tunnel junction (for a given memory density), with the aim of improving the thermal stability of the magnetization of the storage layer. Indeed, in MRAMs of sufficiently small dimensions to have a macrospin type behavior (typically below 40 nm lateral dimension), the thermal stability factor of the memory varies substantially proportional to its surface. The fact of having flared pillars, with a section at the top larger than at their base, makes it possible to maximize the surface of the magnetic element for a given total area per memory point and thus maximize the thermal stability of the magnetization of the storage layer. However, care will be taken to ensure that the magnetostatic interactions of pad to pad do not become too strong, because of the proximity of the edges of neighboring junctions.
[0034] The step F6 represented by FIG. 4F consists of filling with an electrically insulating material 150 the space between the vertical structures formed by the pillars 110, storage elements 120 and superposed covering elements 130. Various techniques of the microelectronic industry make it possible to fill high form factor structures (type STI, FinFET, "damascene" gate transistor, etc.) and / or with overhanging flanks with dielectric material (generally an oxide). In particular, the gas phase deposition of liquid dielectric films may be mentioned. Liquid dielectrics are similar to a gel having the flow characteristics of a liquid. By exploiting this technique, it is easy to fill structures with form factors greater than 10, even up to 30. The liquid dielectric material for filling the inter-ply trenches of FIG. 4F can be chosen from Si 3 N 4, SiO 2 , SiOxCy1-1 ,, SiOxHy and SiOxNyHz. These materials are chosen for their electrical resistivity (advantageously p> 0.1 Q.cm) so that the leakage currents between memory points are minimized. For example, to form a liquid silicon oxide, the substrate is simultaneously exposed to a gaseous precursor containing silicon and an oxidizing gas. The gas containing the silicon and the oxidizing gas are either mixed before introduction into the reactor or injected separately into the reactor. The silicon-containing precursor may be an alkoxysilane, for example Hx-SiOR) y where x = 0-3, x + y = 4 and R denotes an alkyl group. Silane (SiH4) and its derivatives, such as tetraethoxysilane (TEOS), triethoxysilane (TES), trimethoxysilane (TriMOS), lo methyltrimethoxysilane (MTMOS), dimethyldimethoxysilane (DMDMOS), diethoxysilane (DES), dimethoxysilane (DMOS), hexamethoxydisilane (HMODS) and triphenylethoxysilane, or alternatively tetraoxymethylcyclotetrasiloxane (TOMCTS), octamethylcyclotetrasiloxane (OMCTS), methyltriethoxyorthosilicate (MTEOS), tetramethylorthosilicate (TMOS), 1- (triethoxysilyl) -2 15 (diethoxymethylsilyl) ethane and tri-t-butoxylsilanol are other examples of silicon-containing precursors. The oxidizing gas may be ozone (O 3), hydrogen peroxide (H 2 O 2), oxygen (O 2), water (H 2 O), methanol, ethanol, isopropanol or nitric oxide ( NO, N20). The temperature of the substrate and the working pressure in the reactor make it possible to adjust the deposition rates. Generally, the temperature of the substrate is between -30 ° C and 100 ° C (a low temperature makes it possible to increase the deposition rate). The pressure is for example between 100 mT and atmospheric pressure. The advantage of this technique over other gas phase deposition techniques is the absence of voids or cavities in the layer of dielectric material 150. Nevertheless, the presence of voids in the interplate space is not prejudicial, as long as a flat and continuous surface is obtained at the end of step F6. The presence of voids between the pads may even present advantages in certain situations. For example, in the case of PCRAMs, these voids can reduce crosstalk phenomena between the pillars by limiting lateral thermal diffusion. In return, the vertical structures may be more fragile. Physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) techniques form layers of uniform thickness and are therefore able to form voids in structures with high form factor, especially when they have recessed flanks (because they quickly lead to a pinch at the top of the structure).
[0035] An alternative to gas phase processes is spin deposition. In this case, a sol-gel precursor is diluted in a solvent and deposited in liquid form on the rotating substrate. Under the effect of the centrifugal force, the liquid is distributed uniformly over the surface of the substrate. The precursors polymerize and the solvent evaporates to form a dielectric material called "Spin On Glass" (SOG). The thickness of the deposited layer is controlled by the viscosity of the material and the rotational speed of the substrate. The materials thus produced may be silicas or silicones of poly-methylsiloxane, poly-metylsilsesquioxane, polyoxycarbosilane or poly-dimethylsiloxane type. They may also be polymers, such as planarizing resins, for example that marketed by the company "Honeywell" under the name "ACCUFLO". Advantageously, a barrier layer (eg Si3N4) may be deposited on the vertical structures prior to filling by the dielectric material 150, to avoid contact of these structures with the oxidizing environment. The barrier layer preferably has a thickness of between 3 nm and 5 nm. It makes it possible to block the diffusion of the oxidizing species, without the dimensions of the patterns being too impacted. A method of the ALD or PEALD type is preferred to ensure full coverage of the surfaces, including the recessed flanks.
[0036] A partial filling of the trenches is possible, insofar as the electrical insulation is ensured even in the presence of voids. This can make it possible to reduce the interplug conductance and thus to minimize the risk of crosstalk between the pads.
[0037] With all of the above-mentioned deposition techniques, it is difficult to directly obtain a flat surface at the top face of the cover elements 130. Therefore, it is preferable to completely cover the vertical structures with the dielectric material and eliminate then the excess material. To do this, it is possible to use a mechano-chemical planarization method or etch back etching (typically CF4, CHF3, CH2F2, C4F8 or C4F6) when the deposition of the dielectric material already tends to produce a planar layer. Conventionally, the polishing or plasma etching process is stopped when the cover material 130 is reached. This can be done by controlling the polishing / etching conditions, knowing the etch rate and the thickness of the material to be etched, or by detecting the end of etching during the process (e.g. by reflectometry or optical emission spectroscopy).
[0038] Finally, in step F7 of FIG. 4G, a level of contact or metallization is formed on the flat surface obtained at the end of step F6. Each electrical contact 140 is placed at the top of a vertical structure on the cover element 130, and preferably in the center thereof. The contacts 140 are obtained in a conventional manner by means of a so-called "partitioned" process (deposition of a layer of conducting material, structuring by photolithography and then etching), by a "damascene" type method or by a lifting process ("lift" -off "in English). According to an alternative embodiment of the steps F6 and F7 shown in FIG. 5, the dielectric filler material 150 is deposited on the substrate 100 until it completely covers the vertical structures. Then, the contacts 140 are formed according to a "damascene" approach within the material 150 itself. Cavities are opened in the material 150 which open out onto the covering elements 130, and these cavities are then filled with metal (typically copper or copper). aluminum) and finally the excess metal is removed by CMP. Thus, in this alternative embodiment, the electrical contacts 140 are included in the dielectric material filler layer 150, and not in an additional dielectric layer deposited on the filler layer. The planarization step (by CMP or plasma etching), described in connection with FIG. 4F and allowing the filling layer 150 to be flush with the level of the covering elements 130, can then be omitted. It can be seen in the sectional view of FIG. 5 that, when they are made according to the "damascene" method, the electrical contacts 140 and the via conductors 102 of the substrate 100 also have a flared shape, with a section at the base smaller than at their summit. By their shape, the damascene-type via conductors could therefore serve as a support for the variable resistance storage elements.
[0039] Thus, in a third embodiment of the resistive device, the flared conductive pillars are constituted by electrical interconnection via damascene type. In FIG. 6, the pillars are advantageously formed by the upper part of the via conductors 102 'belonging to the last interconnection level of the substrate 100 (before the memory points). In other words, the via conductors 102 'are extended outside the dielectric layer 101 and serve as a support for the deposition of the storage elements 120 and the cover elements 130, before being surrounded by the dielectric filler material 150.
[0040] Alternatively, the conductive pillars may be formed by damascene-type interconnection vias distinct from the interconnection via 102 of the dielectric layer 101. FIGS. 7A to 7C represent steps F1 'to F3' of a method for manufacturing this last variant embodiment of the resistive device. In step F1 'of FIG. 7A, vertical damascene interconnection structures 110' are formed in an additional dielectric layer 103 disposed on the substrate 100, and more particularly on the dielectric layer 101 containing the interconnection via 102. First, the dielectric layer 103 of thickness tox is deposited on the substrate 100. The thickness of the tox is preferably between 4 nm and 400 nm. Then, cavities are etched in the dielectric layer 103 to the substrate 100, preferably by a plasma etching process. Cavities with slightly oblique flanks (this profile facilitates the metallization step) can be obtained by a fluorocarbon gas plasma (CxHyFz) optionally diluted in N2 and / or Ar. Fluorocarbon layers are then formed on the flanks of the units. engraved. Finally, a conductive material is deposited on the dielectric layer so as to completely fill the cavities and the excess of conductive material outside the cavities is removed by chemical mechanical polishing (CMP). The interconnection structures 110 'can be obtained by a "single damascene" or "double damascene" method. In the "simple damascene" process, a single pattern (eg via or line) is formed and then filled with metal in the dielectric layer 103, while the "double damascene" process simultaneously fills two superimposed patterns, for example a via d ' interconnection and an interconnection line covering the via.
[0041] The interconnection structures 110 'are located at the locations where a memory point is desired, in contact with the interconnection via 102 of the substrate 100. Together, they conduct the electric current between the memory points and the read circuit located in the substrate 100. The distance between two consecutive interconnection structures 110 'is preferably equal to or greater than 3F, where F is the smallest dimension attainable by photolithography. Preferably, the conductive material of the interconnection structures 110 'is chosen from copper, tantalum, tungsten, titanium nitride and aluminum, or a combination of these materials (for example Cu surrounded by TiN), because of their low electrical resistivity (p <104 A.cm). The additional dielectric layer 103 may consist of a silicon oxide (SiO 2, SiOCH), a silicon nitride (Si 3 N 4, SiCN) or an insulating polymer material (for example materials sold by the company "Dow Chemical" under the name " SiLK "and by the company" Honeywell "under the name" FLARE "). It can also be composed of two different insulating materials, thus forming two sub-layers, for example a lower SiCN underlayer and an upper underlayer. The lower sub-layer advantageously acts as a barrier to the diffusion of the metal constituting the interconnection structures 110 '(and other interconnection patterns formed simultaneously, type via or line) to the substrate.
[0042] Step F2 'of Figure 7B is to thin the dielectric layer 103, so as to partially release the interconnection structures 110'. Pillars of flared shape are thus obtained which stand vertically on the substrate 100. Their top is free, while their base is buried in the dielectric layer 103, which improves their maintenance and ensures electrical contact with the underlying vias. . Advantageously, the thickness of material removed in step F2 '(the height of the pillars measured from the upper face of the remaining dielectric layer 103 to the vertices) is much greater than the cumulative thickness of the storage elements and coverage that will be deposited subsequently, for example 1.2 times the cumulative thickness of the storage and coverage elements.
[0043] In an alternative embodiment, the dielectric layer 103 is completely removed. The pillars stand on the substrate 100, even in the absence of the layer 103 (then the entire structure will be consolidated by the dielectric filler material 150).
[0044] The removal of the dielectric material 103 is preferably carried out by an isotropic and selective etching relative to the conductive material of the interconnection structures 110 ', in order to release the flanks of the pillars over the entire etched thickness and not to increase the surface roughness, in particular on their upper face intended to receive a storage element. By way of example, in the case of an insulator of the SiO 2 type, the removal step can be carried out wet by means of a solution of hydrofluoric acid or hydrofluoric acid in the vapor phase. For a carbon-based material, an oxygen-based reactive plasma may be used. The combination of an oxygen plasma and a chemical etching of hydrofluoric acid makes it possible to etch a porous material of the SiOCH type. Finally, in the case where the additional dielectric layer 103 containing the interconnection structures 110 'is composed of two different materials, the thinning step F 2' can be performed by etching the entire upper sub-layer, while the bottom sub-layer serves as a stop layer to this etching. The thickness of the removed dielectric material can be controlled by the etch time, knowing the etch rate (except in the case of a selective stop sublayer, where such control is not necessary). FIG. 7C represents the PVD deposition step F3 'of the storage elements 120 and the covering elements 130 at the vertices of the interconnection structures 110'. Step F3 'is identical to step F5 previously described in connection with FIG. 4E, although the pillars have not been obtained in the same way. At the end of the step F3 ', residual deposits 160 are located on the thinned dielectric layer 130, between the interconnection structures 110'. These residual deposits 160 do not disturb the operation of the device. The steps F6 and F7 of the manufacturing method of FIGS. 4A to 4G (filling by the dielectric material and formation of the electrical contacts), as well as their variant represented by FIG. 5, can be carried out at the end of the deposition step. F3 ', according to the same procedures. If it is desired to form pillars according to the embodiment of FIG. 6, that is to say by reusing the via conductors 102 rather than creating an additional level of interconnection, only the dielectric layer 101 is used. Step F1 'then comprises the formation of the damascene-type via conductors 102 in the dielectric layer 101 and, in step F2', the dielectric layer 101 is thinned to release the conductive pillars. There is therefore no additional dielectric layer 103 in this embodiment and the last level of interconnection of the substrate 100 before the memory points is sized to form the pillars. To electrically insulate the sidewalls of the pillars in this third embodiment, a layer of insulating material (Si3N4, Hf02, SiOCH ...) can be deposited in the cavities during the formation of the damascene interconnection structures. This deposit takes place before filling with the conductive material. A method of CVD, PECVD, ALD or PECVD type is advantageously used, so that the insulating layer perfectly fits the side walls of the cavities and covers them homogeneously. This layer, or coating ("liner" in English), preferably has a thickness of between 2 nm and 5 nm, in order to avoid an excessive increase in the resistivity of the pillars while properly isolating their flanks. If necessary, the insulating material deposited on the upper face of the dielectric layer 103 may be removed during the planarization step taking place after filling with the metal. Finally, to restore electrical continuity, the insulating material deposited at the bottom of the cavities can be removed by an ion bombardment spraying method (typically an argon plasma). In addition to its electrical insulation function, the coating on the side walls of the cavities can serve as a barrier layer, preventing diffusion of the metal into the dielectric material. At the time of forming the interconnection structures 110 '(step F1'), other interconnection patterns (via or lines) can be formed simultaneously in another portion of the substrate, for example to make contact with the source areas , drain and gate selection transistors. A layer of sacrificial material (eg SiCN, Si3N4) is first deposited on the substrate after step F1 '. Then, it is open in the portion where it is desired to form the memory points. After depositing the resistive material and the covering material, the sacrificial layer is removed by isotropic etching, carrying with it the materials that cover it (by lifting). Advantageously, a dielectric barrier is deposited on the interconnection patterns and the memory points, before the trenches are filled with the dielectric material 150 and the formation of the electrical contacts 140.
[0045] Fig. 8 shows the configuration of the interconnection structures 110 'when formed by a "double damascene" method. The structures 110 'are in two parts, an upper part 110a and a lower part 110b. Parts 110a and 110b each have a constant section. However, the section of the upper part 110a is larger than that of the lower part 110b, which results in a recess. This recess promotes the discontinuity of the deposition of resistive material and the cover material in step F3 '. The upper part 110a formed by a line may be etched in the dielectric layer before the lower part 110b formed by a via ("Trench First Via Last" approach) or after ("Via First Trench Last approach").
[0046] In the sputtering technique used in step F5 (FIG. 4E) for depositing the storage elements at the vertices of the pillars 110, a target consisting of the material to be deposited is bombarded by a plasma, generally based on argon.
[0047] Unless diaphragms are interposed between this target and the substrate during deposition, the chemical species are emitted from the target with a certain angular distribution. The opening angle of this distribution depends in particular on the spraying mode (continuous or radiofrequency), the voltage applied to the target, the pressure of the sputtering gas and the nature of the pulverized material. Typically, this opening angle is between -200 to +200 relative to a direction normal to the target (mid-height measurement). The diaphragms make it possible to increase the directivity of the sputtered species beam, by limiting the angular aperture. In this case we speak of collimated sputtering.
[0048] When the cathodic sputtering of step F5 is not collimated, the layer deposited at the top of each pillar has a rounded shape at the edges of the pillar, rather than at right angles (see Fig.4E), because of the angular dispersion of the sputtered species beam. This rounded shape results from a shading effect occurring during the deposition at each pillar. Here, it is proposed to take advantage of this rounded shape at the edges of the pillars in order to create local variations in thickness and / or chemical composition in the storage elements. This makes it possible, in particular, to confine the electric current in the central part of each memory point, far from the edges where the risk of encountering structural defects is greatest (but nevertheless lesser compared to the plasma etching and IBE methods of the prior art ). The thickness and composition gradients are advantageously created by varying the incidence of sputter deposition. Various examples of storage elements implementing this principle are described below.
[0049] FIGS. 9A to 9C show in detail the formation of an MRAM magnetic tunnel junction at the top of a pillar 110. The stack of layers that constitutes the magnetic tunnel junction comprises, for example, a lower electrode containing the reference magnetic layer. 121 CoFeB alloy, a tunnel barrier layer 122 MgO and a magnetic storage layer 123 alloy CoFeB. A cover element 130, for example tantalum, is added over the stack for the purpose of making higher electrical contact.
[0050] In FIG. 9A, the lower electrode containing the reference layer 121 made of CoFeB is deposited by non-collimated cathodic sputtering at a normal incidence at the plane of the substrate 100, parallel to the axis of symmetry 111 of the pillar 110 (the latter being oriented perpendicular to the substrate 100). The layer 121 then comprises a flat portion 121a in the center of the upper face of the pillar 110 and rounded edges 121b partially covering the sidewalls of the pillar 110. The MgO tunnel barrier layer 122 is then deposited on the layer reference numeral 121 (FIG. 9B). The deposition of MgO is advantageously carried out by cathodic spraying in oblique incidence at an angle θ measured with respect to the axis 111 of the pillar 110, for example equal to 45 °. As a result, the material is deposited more slowly on the central portion 121a of the layer 121 than on the rounded edge 121b disposed on the same side as the MgO source (right edge in Figure 9B). Indeed, in cathodic sputtering, the deposition rate is proportional to the cosine of the angle α between the normal to the surface on which the flow of material is deposited and the direction of propagation of this flux. However, the angle a is 45 ° at the level of the flat portion 121a (center = 0 = 45 °), while approaching the rounded edge 121b, the angle a decreases to 0 ° in the middle of the 'rounded EX edge = 0 °). During the deposition, the substrate which supports the pillar 110 is advantageously rotated. This makes it possible to obtain a symmetrical tunnel barrier layer 122 having a central portion 122a which is thinner than its edges 122b (because the deposition rate is lower there), as illustrated in FIG. 9C. The formation of the tunnel junction is completed by the deposition of the CoFeB storage layer 123 on the tunnel barrier layer 122, then the tantalum cover element 130 is deposited on the storage layer 123. These two deposits are preferably made by collimated cathodic sputtering at a normal incidence, in order to prevent the layers 123 and 130 from projecting onto the sides of the pillar 110 (which could cause a short circuit of the magnetic tunnel junction).
[0051] Thus, a lateral thickness gradient of the MgO tunnel barrier layer 122 can be obtained by varying the incidence of the deposit. This gradient is particularly advantageous during operation of the MRAM. Indeed, when a voltage is applied on both sides of the magnetic tunnel junction, the electric current flows through the tunnel barrier layer 122 and preferentially in the center thereof, that is to say in the portion 122a where its thickness is the lowest (Fig.9C). Thus, it is possible to reduce the impact of possible edge defects on the electrical and magnetic properties of the memory cells and thus reduce the variability of one memory point to another in an MRAM.
[0052] FIGS. 10A and 10B show another example of obtaining a lateral thickness gradient, this time in an OxRAM type storage element. In this type of memory point, a conductive path is formed reversibly through an oxide, by accumulation of oxygen vacancies. The typical stack comprises a first electrode 124 (for example TiN), an oxide layer 125 (eg HfO 2) and a second electrode 126 (eg Ti / TiN). Again, to minimize the variability from one memory point to the other, it is advantageous to shape the memory point so that the conductive path is formed in the central portion of the memory point, away from the edges that are likely to contain faults. This can be achieved by sputtering the HfO2 oxide at an oblique angle (e.g. 45 °) by rotating the substrate on itself, as shown in FIG. 10A. In fact, this deposition mode makes it possible to obtain an oxide layer 125 having a thinner thickness in its central portion 125a than on its edges 125b (FIG. 10B). The electric current is then concentrated in the center of the storage element, as in the tunnel barrier layer of the previous example. Rather than obtaining a local variation in thickness, it is possible to seek to modify locally the composition of an alloy used in the manufacture of the storage elements. FIGS. 11A and 11B show an example of a magnetic tunnel junction for STT-MRAM magnetic spin transfer memory. In this type of memory, it is advantageous to use the CoFeV alloy as a storage electrode, since vanadium (V) is known to reduce the Gilbert damping coefficient. This makes it possible to reduce the spin transfer write current (the write current is proportional to this damping coefficient). Moreover, it is known that the incorporation of vanadium into the CoFe alloy has the effect of reducing the magnetic moment of iron. The magnetic properties of the electrode could therefore be modulated by varying the vanadium content in the CoFeV alloy.
[0053] To achieve such a result, the electrode can be deposited by simultaneous sputtering of a CoFe alloy in normal incidence (non-collimated) and vanadium oblique incidence (for example at 45 °), while rotating the substrate on himself (Fig.11A). This results in a layer 127 of CoFeV alloy whose vanadium content is lower in its central portion 127a than on its edges 127b (Fig.11B), thanks to a deposition rate of vanadium lower in the center than on the edges . The electrode 127 is then formed of a CoFeV alloy of a first composition on the central portion of the pillar 110 (for example C060Fe20V20) and a CoFeV alloy of a second composition at its periphery, having a higher concentration of vanadium (for example C040Fe13V47). This latter alloy can also become non-magnetic if it is very rich in vanadium, which again avoids being sensitive to defects in pillar edges, such as local variations of magnetic anisotropy. Finally, the example represented by FIGS. 12A and 12B relates to a memory storage element PCRAM. In a PCRAM memory, the storage material is a phase-change material, for example of the GeSbTe type (different compositions of this alloy are possible), having a stable structure at ambient temperature, either in an amorphous state or in a crystallized state. . These two states have different electrical resistances, the amorphous state being much more resistive than the crystallized state (sometimes 1000 times more resistive). The reading is performed by measuring the resistance level of the phase change material by means of an electric current flowing therethrough. The writing of the memory point is done by applying a shaped current pulse adapted to the state that one wishes to write. A narrow pulse followed by quenching rapidly from the liquefaction temperature of the material leads to the amorphous state. A long pulse at a temperature just below the crystallization temperature followed by a slower cooling leads to the crystalline state. Moreover, it is known that by increasing the concentration of germanium (Ge) in the alloy, the crystallization temperature and the electrical resistivity in the crystallized state increase. A layer of phase change material having two different compositions of the GeSbTe alloy can be obtained by directing towards the top of the pillar 110 a flow of SbTe (non-collimated) at a normal incidence and a Ge flux at an oblique incidence ( 45 °) simultaneously, as shown in Figure 12A. This mode of deposition forms a layer 128 of GeSbTe whose central portion 128a is less rich in germanium than its edges 128b (Fig.12B). Since the alloy at the edges 128b has a higher crystallization temperature than the center, the active part of the memory point is limited to the central portion 128a of the memory layer 128. As before, this makes it possible to standardize the electrical properties between the different memory points. Of course, other streams than those described above can be used. For example, a variable germanium content can be obtained with a normal incidence flux of Sb2Te3 and an oblique incident flux of GeTe. On the other hand, by increasing the antimony (Sb) content in the GeSbTe alloy, the writing speed of the PCRAM memory point increases and the amorphous-crystalline transition temperature decreases. By depositing antimony at normal incidence and the GeTe alloy at oblique incidence, a richer Sb alloy can be obtained in the center of the pillar than at its edge. Thus, the amorphous / crystallized transition occurs preferentially in the center of the pad. More generally, a lateral thickness gradient can be obtained by cathodic sputtering of a chemical species at oblique incidence, whereas a lateral gradient of chemical composition can be obtained by simultaneous sputtering of at least two chemical species. different with different bearings, one being oblique and the other normal. Preferably, the inclination angle θ of the oblique flow is between 20 ° and 70 °. Note also that obtaining a thickness gradient and / or chemical composition is independent of the shape of the pillars and the manner in which they were obtained. These deposition modes of the storage element are indeed applicable regardless of the profile of the flanks: inward flanks (i.e. overhanging, notch or arc), straight or even outgoing. In addition, it is not necessary to rotate the substrate on itself if one does not try to obtain a thickness gradient and / or symmetrical composition, i.e. on all the edges of the pillars.
[0054] The use of flared abutments as a support for the deposition of the resistive material widens the field of application of non-volatile memories. In fact, besides the fact that the production of an OxRAM, CBRAM, PCRAM or MRAM memory is facilitated, it is now possible to form a hybrid memory, i.e. which comprises two matrices of memory points of different technologies on the same substrate. By way of example, it is possible to associate a matrix of MRAM magnetic memory points with a matrix of PCRAM memory points confined in volume. Confined PCRAMs are a class of phase-change memories in which the active part of the phase-change material is located on a side wall of a spacer of dielectric material. Such a structure makes it possible to optimize the electrical consumption of the memory, in particular by reducing the write current of the insulating state ("reset" current). Confined PCRAMs have been the subject of many studies, including the article ["A Scalable Volume-Concluded Phase Change Memory using Physical Vapor Deposition", SC Lai, Symposium of VLSI Technology, 2013], but have never been associated with another type of memory so far. The advantage of the MRAM / PCRAM hybrid memories is that a complete solution of non-volatile memory is obtained in the same component, which brings together the forces of each type of memory, here the endurance and the speed of operation of the MRAMs of a on the other hand, the low consumption and the high integration density of the confined PCRAMs on the other hand. Such hybrid memories make it possible to replace volatile memories in many situations. To manufacture a hybrid MRAM / PCRAM memory, a first portion of the substrate containing flared conductive pillars is dedicated to the formation of the magnetic memory points, according to the method described with reference to FIGS. 4A to 4G. The PCRAM memory points are formed in a second portion of the substrate, which also contains flared conductive pillars. In other words, the conductive pillars are distributed between these first and second portions of the substrate. The conductive pillars of the second portion are covered with a phase change material, while magnetic tunnel junctions are formed at the tops of the pillars of the first portion. A method for manufacturing the confined PCRAM template will now be described below with reference to Figs. 13A to 13F. This method and that of FIGS. 4A to 4G share a large number of characteristics (the elements in common bear the same reference signs). In fact, they are compatible with each other and make it possible to integrate the two types of memory on the same substrate. The information given above on any of the steps of FIGS. 4A and 4G, in particular their operating modes, are applicable as soon as one of these steps is taken up in the manufacturing process of the confined PCRAM matrix, even partially. We will therefore focus below to highlight the differences between the two processes, rather than repeat this information.
[0055] In step S1 of FIG. 13A, the first conductive layer 300 intended to form the conductive pillars is deposited on the substrate 100 of FIG. Advantageously, the conductive layer 300 is covered with a protective layer 320 preventing the formation of an insulating oxide or nitride, for example ruthenium (in the case of an oxide). Finally, a dielectric layer 330 is deposited on the protective layer 320. During the step S2 shown in FIG. 13B, spacer pads 331 are formed in the dielectric layer 330 by photolithography and etching. The etching is performed for example by reactive plasma etching with stopping on the underlying ruthenium layer 320. It can be strongly anisotropic, in which case the spacers 331 have sidewalls perpendicular to the plane of the substrate. The dielectric material of the spacers 331 is advantageously a nitride (eg SiN), to prevent it from oxidizing the phase-change material which will later cover these pads. Preferably, the spacer pads 331 have a width equal to F and are separated by trenches of width equal to 2F. They are therefore spaced periodically, like the via conductors 102 of the substrate 100 (their period equaling 3F).
[0056] During the same step S2 (FIG. 13B), an etching mask 310 '(hard or resin mask) is formed on the spacer pads 331 and a part of the ruthenium protection layer 320. The mask 310 'fulfills the same function as the mask 310 of FIG. 4B, except that it here marries the surface topography created by the etching of the dielectric layer 330. The solid parts of the mask 310', located at the plumb conductors 102, are straddling between the protective layer 320 and the spacer pads 331. Finally, the layers 300 and 320 are etched through the mask 310 'to form the conductive pillars 110. The etching conditions are chosen from way to form overhanging flanks, as previously described in connection with Figure 4C. At the end of step S2, flared pillars 110 are obtained, the upper face of which is covered by the protective layer 320 made of ruthenium, itself being partially covered by the spacer studs 331. Preferably, the spacers 331 are all located on the same side of the pillars 110 (for example the left side in FIG. 13B) and do not protrude from the edge of the pillars 110. FIG. 13C represents the optional step S3 for oxidizing the sidewalls of the pillars 110 , after removal of the engraving mask. When this step takes place, the protective layer 320 allows the upper face of the pillars 110 to remain electrically conductive. In the example above, a ruthenium oxide 210 is formed in the layer portion 320 disposed at the top of each pillar 110 and not covered by the spacer stud 331. Of course, rather than a material whose oxide is conductive, the protective layer 320 may be formed of a material whose nitride (reference 210) is conductive (in this case, step S3 is a nitriding) or a noble metal (oxidation or nitriding leaves intact layer 320). Furthermore, an oxide (or nitride) insulating layer 200 is formed on the flanks of the pillars 110. In S4 (FIG. 13D), the phase change material (PCM) is deposited by PVD, preferably by sputtering, at vertices of the pillars 110 on the one hand, and between the pillars 110 on the other hand. A layer 340 of PCM covers the spacers 331, including their side walls (due to the angular opening of this deposition mode), and the layer 210 of ruthenium oxide. Residual deposits 160 of PCM material are formed at the bottom of the trenches separating the pillars 110. The PVD deposit makes it possible to obtain a layer of PCM 340 of substantially constant thickness on the side walls of the spacer studs 331. spacer pads 331 (ie the thickness of the dielectric layer 330) is advantageously between 50 nm and 100 nm. This makes it possible to obtain good thermal confinement and thus to minimize the energy to be supplied during the operation of the memory.
[0057] The programming current of the memory point decreases as the thickness of the PCM 340 layer decreases. The thickness of the PCM layer 340 on the side walls of the spacers 331 is preferably between 4 nm and 50 nm so that the power consumption of the memory device is controlled. The layer 340 deposited by sputtering generally has a ratio of about 2: 1 between the thickness deposited on the upper face of the spacer pads 331 and the thickness deposited on their side walls. This ratio can be decreased by forming spacers 331 with inclined side walls rather than vertical ones. The ratio then tends to 1: 1 when the angle of inclination of the side walls (relative to the upper face of the studs 331) is close to 180 °. The phase change material is an alloy based on chalcogenide materials, such as germanium, antimony and tellurium (eg GeSbTe, GeTe, GeSb, SbTe). This alloy can be doped with one or more other chemical elements, such as N, C, Si, Se, In, Sn, Ag, or combined with a dielectric material such as SiO, SiN and TiO.
[0058] In step S5 shown in FIG 13E, the trenches between the conductive pillars 110 and between the spacer pads 331 are filled by the dielectric material 150. Previously, a nitride barrier layer (eg SiN) may be deposited on the PCM material, to protect it from oxidation by the dielectric material (when it is an oxide). This barrier layer is particularly advantageous in the case of confined PCRAMs because the active layer of PCM is thin (4-50 nm). As before, it is preferable to completely cover the nanostructures formed on the substrate 100 with the dielectric material 150, then flatten the surface of the material by polishing until reaching the surface of the spacer pads 331 and the layer of PCM 340 which cover their flanks. Finally, at S6 (FIG. 13F), a metallization level 350 is formed on the flat surface of the dielectric filler material 150. This level 350 may comprise metal lines 140, forming electrical contacts for several memory points simultaneously, embedded in a dielectric layer 141. Preferably, each metal line 140 of the level 350 covers at least a portion of a spacer pad 331 and the PCM layer 340 disposed against one of the side walls of this pad.
[0059] Preferably, the level of metallization 350 is made according to a "damascene" method. The metal lines 140 advantageously comprise a first metal layer 140a having a good grip on the phase change material (eg Ti, Ta). This first layer 140a covers the bottom and the side walls of the trenches formed in the dielectric layer 141. Then, a second metal layer 140b, having a conductivity greater than that of the tie layer 140a (eg Al), constitutes the heart of the metal lines 140.
[0060] This level of metallization 350 is generally one of the reading buses of the memory points, either the word bus or the bit bus, while the interconnection patterns 102 of substrate 100 are via drivers as seen previously. The metal lines 140 of the level 350 may extend perpendicular to the sectional plane of Fig. 13F or parallel to this section plane, depending on how the other metallization level (i.e. via 102) has been defined. Fig. 14 shows, by way of example, two confined PCRAM memory points located in the sectional plane A-A of Fig. 13F. Each memory point comprises successively a conductive pillar 110, a protective layer Ru0 210 and a layer of PCM material 340. The two memory points are electrically connected by means of the upper metallization level 350 but can nevertheless be individualized thanks to the interconnection patterns 102 of the substrate 100.
[0061] A number of steps of the process for manufacturing the MRAM memory matrix (FIGS. 4A-G) and the process for manufacturing the confined PCRAM memory matrix (FIGS. 13A-F) can be shared in order to efficiently produce memories. MRAM / PCRAM hybrids. Since the two types of memory are based on flared conductive pillars, the steps of forming these pillars in the first portion and the second portion of the substrate can be performed simultaneously. The step of filling with the dielectric material 150 (deposit followed by possible planarization) and the step of forming the upper electrical contacts 140 are other examples of steps that can be shared.
[0062] Therefore, only the steps of formation of the spacer pads 330 and the deposition of the phase change material are specific to the method of manufacturing the confined PCRAM memory matrix. During these steps, the first portion of the substrate reserved for the magnetic memory points may be covered by a sacrificial material, and vice versa when it is the magnetic memory points to be formed. The nitride layer 330 is thus limited to the portion reserved for the PCRAM matrix.
[0063] During the step S5 of opening the contacts (Fig.13E), chemical mechanical polishing (CMP) can alter the layer 340 of phase change material. Indeed, there is a phenomenon of over-etching the PCM material, due to the fact that the abrasive solution ("slurry") planarization chemically reacts with the PCM material. However, this over-etching can be detrimental to form a quality electrical contact between the confined layer of PCM material and the metal line of the upper interconnection level 350. FIG. 15 represents another, more advantageous, way of accessing the confined layer 340 of PCM material (and at the spacer portion 331) to make contact therewith. In this variant embodiment of step S5, the mechano-chemical planarization of the dielectric material 150 is replaced by a plasma etching step. This etching step is here particularly simple to implement, even when the memory points are very close to each other, since the memory points are already individualized thanks to the use of the pillars. The constraints on the engraving mask can therefore be relaxed.

权利要求:
Claims (28)
[0001]
REVENDICATIONS1. Resistive device comprising: a substrate (100); a plurality of variable electrical resistance storage elements (120); characterized in that it comprises a plurality of electrically conductive pillars (110, 102 ', 110') disposed on the substrate and spaced from each other, each conductive pillar (110, 102 ', 110') having a section at its base smaller than its top, and in that the storage elements (120) are arranged at the vertices of the conductive pillars, so that each storage element (120) is supported by one of the conductive pillars (110, 102 ', 110').
[0002]
2. Device according to claim 1, wherein the conductive pillars (110, 102 ', 110') have flanks covered with a layer of electrically insulating material (200).
[0003]
3. Device according to one of claims 1 and 2, wherein the section of each conductive pillar (110, 102 ', 110') varies continuously and strictly increasing from the base to the top of the conductive pillar (110).
[0004]
4. Device according to any one of claims 1 to 3, wherein the substrate (100) comprises a dielectric layer (101) traversed by interconnection patterns (102) above which are located the conductive pillars (110, 110 ').
[0005]
5. Device according to any one of claims 1 to 3, wherein the substrate (100) comprises a dielectric layer (101) traversed by interconnection patterns (102 '), said interconnection patterns extending further. outside the dielectric layer to form the conductive pillars.
[0006]
6. Device according to any one of claims 1 to 5, wherein the conductive pillars (110, 102 ', 110') are separated from each other by a dielectric material 302 74 5 44 (150).
[0007]
7. Device according to any one of claims 1 to 6, wherein the storage elements (120) are formed of a stack of MRAM, PCRAM, CBRAM, OxRAM, or logic type MLU.
[0008]
8. Device according to any one of claims 1 to 7, wherein the substrate (100) comprises first and second portions on which are distributed the conductive pillars (110), the storage elements (120) of the first portion 10 being of the MRAM type and the storage elements (120) of the second portion being of the confined PCRAM type.
[0009]
9. A method of manufacturing a resistive device comprising the steps of: depositing (F1) a first electrically conductive layer (300) on a substrate (100); - forming (F2) an etching mask (310) on the first conductive layer (300); - etching (F3) through the mask (310) the first conductive layer (300), so as to obtain a plurality of electrically conductive pillars (110) spaced from each other and having a section at their base smaller than at their summit; forming (F5) by physical vapor deposition of the variable electrical resistance storage elements (120) at the vertices of the conductive pillars (110), so that each storage element is supported by one of the conductive pillars.
[0010]
The method of claim 9, wherein the first conductive layer (300) is etched by reactive plasma etching. 30
[0011]
11. The method of claim 10, wherein the first conductive layer (300) is etched by an inductive plasma generated by applying a radiofrequency electromagnetic field with a power of between 100 W and 500 W under a bias voltage of between 15 V and 1 kV.
[0012]
12. The method of claim 10, wherein the etching of the first conductive layer (300) comprises successively: an anisotropic etching of an upper portion of the first conductive layer (300), configured so as to obtain covered vertical flanks. by a passivation layer; an isotropic etching of a lower portion of the first conductive layer (300), the isotropic etching of the vertical flanks of the upper portion being prevented by said passivation layer.
[0013]
13. The method of claim 10, wherein the first conductive layer (300) comprises upper and lower sub-layers formed of different conductive materials, the etching of the first layer (300) comprising successively: an anisotropic etching of the sub-layer. upper layer selectively with respect to the lower sub-layer; an isotropic etching of the lower sub-layer selectively with respect to the upper sub-layer.
[0014]
The method of any one of claims 9 to 13, wherein the storage elements (120) are formed of one or more sputtered layers.
[0015]
The method of claim 14, wherein the storage elements (120) comprise a first layer (121, 124) deposited by non-collimated sputtering at normal incidence relative to the substrate (100) and a second layer (122). , 125) deposited on the first layer (121, 124) by cathodic sputtering at oblique incidence.
[0016]
The method of claim 14, wherein the storage members (120) comprise a first noncollimated sputtered layer at normal incidence relative to the substrate (100) and a second layer (127, 128) formed by sputtering simultaneously. a first chemical species under normal incidence and a second chemical species under oblique incidence.
[0017]
The method of any one of claims 9 to 16, further comprising the steps of: depositing (F5) a second electrically conductive layer on the storage elements (120), whereby coverage elements ( 130) superimposed on the storage members (120); filling (F6) the space between the conductive pillars (110), between the storage elements (120) and between the covering elements (130) by a dielectric material (150); forming (F7) an electrical contact (140) on the surface of each cover element (130).
[0018]
18. A method according to any one of claims 9 to 17, further comprising a step (F4) of forming a layer of electrically insulating material (200) on the flanks of the conductive pillars (110).
[0019]
The method of claim 18, wherein the material of the first conductive layer (300) is selected from tantalum, tungsten, aluminum, titanium, titanium nitride and doped polycrystalline silicon, and wherein the layer of electrically insulating material (200) on the sidewalls of the pillars (110) is obtained by oxidation of the material of the first layer (300).
[0020]
20. The method of claim 19, comprising depositing a layer of noble metal, ruthenium or chromium on the first layer (300), before the step of forming the etching mask (310).
[0021]
The method of claim 18, wherein the material of the first layer (300) is doped tantalum or polycrystalline silicon, and wherein the layer of electrically insulating material (200) on the sidewalls of the pillars (110) is obtained. nitriding the material of the first layer (300).
[0022]
The method of claim 21, comprising depositing a titanium layer on the first layer (300), prior to the step of forming the etch mask (310).
[0023]
23. The method of claim 18, wherein the layer of electrically insulating material (200) on the sidewalls of the pillars (110) is obtained by forming dielectric spacers.
[0024]
The method of any one of claims 9 to 23, wherein forming the storage elements (120) at the apices of the pillars (110) comprises depositing a magnetic tunnel junction in a first portion of the substrate (100). and depositing (S4) a layer of phase change material (340) in a second portion of the substrate (100), the method further comprising forming (S2) spacer pads (331) at the apices of the pillars ( 110) located in the second portion of the substrate, prior to deposition (S4) of the phase change material layer (340).
[0025]
25. A method of manufacturing a resistive device comprising the following steps: - forming (F1 ') vertical interconnection structures (102', 110 ') of damascene type electrically conductive material on a substrate (100), said structures vertically interconnecting being distributed within a dielectric layer (101, 103) and having a section at their base lower than their top; thinning (F2 ') the dielectric layer (101, 103) so as to at least partially release said vertical interconnection structures (102', 110 '); and - forming (F3 ') by physical vapor deposition of the variable electrical resistance storage elements (120) at the vertices of the vertical interconnection structures (102', 110 '), so that each storage element is supported by one of the vertical interconnection structures.
[0026]
The method of claim 25, wherein the dielectric layer (101, 103) is thinned by means of isotropic etching and selective with respect to the conductive material.
[0027]
Method according to one of claims 25 and 26, wherein the damascene-type vertical interconnection structures (102 ', 110') are formed by depositing the dielectric layer (101, 103) on the substrate (100), by etching cavities in the dielectric layer (101, 103), filling the cavities with the conductive material and polishing off the excess conductive material outside the cavities.
[0028]
28. The method of claim 27, further comprising a step of depositing a layer of electrically insulating material (200) on the side walls of the cavities, before filling the cavities with the conductive material.

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FR3027450B1|2014-10-20|2016-11-04|Commissariat Energie Atomique|HYBRID NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE|US10490743B2|2015-09-24|2019-11-26|Nec Corporation|Crossbar switch and method of manufacturing the same and semiconductor device|

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KR20190031806A|2017-09-18|2019-03-27|삼성전자주식회사|Semiconductor device and method for manufacturing the same|

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US10290679B1|2018-03-09|2019-05-14|Globalfoundries Singapore Pte. Ltd.|High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same|

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US10504961B2|2018-03-16|2019-12-10|Micron Technology, Inc.|Methods of forming integrated circuitry|

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US10593728B1|2018-12-10|2020-03-17|Globalfoundries Singapore Pte. Ltd.|Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junctionstructures|

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FR3091033B1|2018-12-21|2021-01-01|Commissariat Energie Atomique|METHOD OF MANUFACTURING A SPINTRONIC DEVICE INCLUDING A THICK ACTIVE MAGNETIC LAYER|

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US10790001B2|2019-01-04|2020-09-29|International Business Machines Corporation|Tapered VA structure for increased alignment tolerance and reduced sputter redeposition in MTJ devices|

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US11177397B2|2020-01-09|2021-11-16|Vanguard International Semiconductor Corporation|Semiconductor devices and methods for forming the same|

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2016-04-22| PLSC| Publication of the preliminary search report|Effective date: 20160422 |

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2016-10-24| PLFP| Fee payment|Year of fee payment: 3 |

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2017-09-21| PLFP| Fee payment|Year of fee payment: 4 |

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2018-10-30| PLFP| Fee payment|Year of fee payment: 5 |

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2021-07-09| ST| Notification of lapse|Effective date: 20210605 |

优先权:

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申请号 | 申请日 | 专利标题

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FR1460073A|FR3027453B1|2014-10-20|2014-10-20|RESISTIVE DEVICE FOR MEMORY OR LOGIC CIRCUIT AND METHOD FOR MANUFACTURING SUCH A DEVICE|FR1460073A| FR3027453B1|2014-10-20|2014-10-20|RESISTIVE DEVICE FOR MEMORY OR LOGIC CIRCUIT AND METHOD FOR MANUFACTURING SUCH A DEVICE|

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PCT/EP2015/073897| WO2016062613A1|2014-10-20|2015-10-15|Method for manufacturing a resistive device for a memory or logic circuit|

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US15/520,132| US10056266B2|2014-10-20|2015-10-15|Method for manufacturing a resistive device for a memory or logic circuit|

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EP15781110.0A| EP3210246B1|2014-10-20|2015-10-15|Method for manufacturing a resistive device for a memory or logic circuit|